Digital circuits, and, more particularly, synchronous digital circuits employ a periodically oscillating signal, i.e., a clock signal for coordinating various functions performed by the synchronous digital circuits. Such functions typically include sampling data that is transmitted within and outside the synchronous digital circuits. The clock signal may be generated by crystal oscillators, voltage controlled oscillators (VCOs), astable multivibrators, and the like. A duty cycle of the clock signal is defined as a ratio of an ON time period of the clock signal to a total time period of the clock signal. For example, when the clock signal has a duty cycle of 75%, the clock signal remains ON for 75% of the total time period, and remains OFF for 25% of the total time period.
Many of the synchronous digital circuits that employ clock and data recovery (CDR) circuits, phase interpolators, phase locked loops (PLLs), and the like for performing data serialization and deserialization use differential clock signals for sampling serialized data. The differential clock signals include first and second differential clock signals that are at a phase difference of 180° with respect to each other. It is imperative that the duty cycles corresponding to the first and second differential clock signals are at 50% for facilitating errorless sampling of the serialized data. Typically, the aforementioned circuits employ a voltage controlled oscillator (VCO) for generating the first and second differential clock signals. Due to changes in physical conditions such as temperature, aging of the VCO, voltage fluctuation, electromagnetic noise, and the like, the duty cycles corresponding to the first and second differential clock signals may deviate from 50%, thereby causing errors in the duty cycles.
The errors in the duty cycles of the first and second differential clock signals can be classified into differential and common errors. The differential errors in the first and second differential clock signals are caused when the duty cycles of the first and second differential clock signals deviate differentially from 50%. The common errors in the first and second differential clock signals are caused when the duty cycles of the first and second differential clock signals deviate equally from 50%. The differential and common errors in the first and second differential clock signals may lead to jitter therein. Jitter may lead to data loss during data sampling.
To overcome the aforementioned problems, the synchronous digital circuits employ duty cycle correction (DCC) circuits. The DCC circuits rectify the duty cycles to 50% duty cycle for facilitating errorless sampling of the serialized data. The DCC circuits known in the art achieve duty cycle correction using charge pumps and integrators. Such DCC circuits employ a negative feedback configuration for adding a DC offset signal to the first and second differential clock signals. Based on the DC offset signal, the DCC circuits generate corrected first and second differential clock signals. However, inclusion of the charge pump in such DCC circuits leads to a complex circuit design thereof. Further, the power consumed by the DCC circuits is high.
Other DCC circuits employ differential amplifiers for rectifying the duty cycles. The differential amplifiers receive the first and second differential clock signals, and generate the corrected first and second differential clock signals by amplifying the difference between the first and second differential clock signals. However, the DCC circuits employing the differential amplifiers fail to rectify the common errors in the first and second differential clock signals, thereby inducing jitter in the first and second differential clock signals.
Hence, it would be advantageous to have a DCC circuit that has a simple design, corrects the differential and common errors in the first and second differential clock signals, and prevents jitter in the first and second differential clock signals.